The present invention relates to a chip internal voltage generating circuit for generating internal voltages for a semiconductor integrated circuit and a semiconductor memory using the internal voltage generating circuit and, more particularly, to a voltage setting circuit for setting a plurality of variable potentials and a semiconductor memory using the voltage setting circuit, which are used, e.g., for a data write/erase multi-level voltage generating circuit for a nonvolatile semiconductor memory.
A single power supply has recently been employed in a semiconductor integrated circuit incorporating an electrically programmable and erasable nonvolatile memory, e.g., an EEPROM or flash memory. When a single power supply is used, an internal voltage generating circuit provided in a chip generates a high voltage required to write or erase data.
Such an internal voltage generating circuit includes a charge pump circuit which generates a high voltage from the an externally applied power supply voltage and a voltage limiter circuit for adjusting the output voltage from the charge pump circuit to a desired voltage value (internal voltage).
In consideration of variations in characteristics of wafers or chips, it is essential to add a trimming circuit to the voltage limiter circuit. In some case, a generated internal voltage may be intentionally stepped up to be used for write or erase operation.
Under the circumstances, it is desired that the voltage range and the step-width of the above voltage limiter circuit can freely be designed in accordance with the application purpose. It is therefore preferable that the above voltage limiter circuit allows arbitrary setting of a set voltage range and the width of voltage steps.
FIG. 7 shows an equivalent circuit of a conventional internal voltage generating circuit for generating internal voltages, such as write and erase voltages in an EEPROM or flash memory.
Referring to FIG. 7, a voltage limiter circuit is connected to an output node 10 of a charge pump circuit (CP) 70 generating a given internal voltage. In this voltage limiter circuit, a load resistor RL having a constant resistance is connected in series to an equivalent resistor R1xe2x80x2 of a trimming circuit 20 for setting the voltage value of output node 10. Resistors RL and R1xe2x80x2 are arranged between the output node 10 of the charge pump circuit 70 and a ground potential Vss.
A comparison output VXXFLG is generated by voltage comparing circuit 13 comparing the potential at a connection node N1 between the resistor elements RL and R1xe2x80x2 with a reference voltage Vref. This comparison output VXXFLG is fed back to the charge pump circuit 70 through a CP control circuit 17 to control the boosting operation of the charge pump circuit 70 so as to make the potential at the connection node N1 equal to the reference voltage Vref. As a result, an output voltage VXX from the output node 10 is controlled to be constant.
FIG. 8 shows an equivalent circuit of a resistance-type potential dividing D/A conversion circuit, which is a conventional arrangement of trimming circuit 20 as shown in FIG. 7.
This trimming circuit comprises division resistors R1-1, R1-2, . . . , R1-m connected in series, MOS transistors T1, T2, . . . , Tm serving as switches, each having one terminal connected to corresponding one of the resistors at one terminal closer to the ground potential and having the other terminal commonly connected to the ground potential Vss, and a decoder circuit 21 for decoding control data B1, B2, . . . , Bn (n-bit data) to supply control signals D1, D2, . . . , Dm for selectively turning on one of the MOS transistors.
The output voltage VXX at the output node 10 of the charge pump circuit 70 in FIG. 7 can be expressed by:
xe2x80x83VXX=Vref+(Vrefxc2x7RL)/R1xe2x80x2xe2x80x83xe2x80x83(1)
As is obvious from equation (1) above, the output voltage VXX can be adjusted by adjusting the resistance value of the equivalent resistor element R1xe2x80x2 in the trimming circuit 20 thereby to change the potential at a connection node N10.
In the circuit arrangements shown in FIGS. 7 and 8, both the absolute value of the output voltage VXX and a voltage step width are determined by the load-resistor element RL and the resistor element R1xe2x80x2 subjected to trimming. In other words, when the resistance values of the resistor element R1xe2x80x2 and the load resistor element RL change, both the value of the output voltage VXX and voltage step width may vary.
If, therefore, the range of the output voltage VXX required is changed, the value of the equivalent resistor element R1xe2x80x2 of the trimming circuit 20 must be determined again to keep the voltage step width unchanged (As for the circuit of FIG. 8, it will be necessary to set again the resistance value of each of the resistors R1-1 to R1-m.) The same problem occurs in the case that only the voltage step width is changed. Further, The same applies to a processed chip. For example, when the resistance values of the resistor elements R1xe2x80x2 and RL are changed by adding or removing interconnections (resistance components) by FIB process, there occurs a problem such that the voltage step as well as the range of the output voltage width is change.
More specifically, in the conventional internal voltage generating circuit shown in FIGS. 7 and 8, the degree of freedom in determining a set voltage range, the minimum set voltage, and the number of voltage steps is low. When the minimum set voltage changes, the voltage step width also changes. In addition, since decoder circuits, each identical to the decoder circuit 21 for generating control signals, are required in accordance with the number of set voltages, the arrangement is complicated, and the number of elements used increases.
For example, to make the voltage limiter circuit generate set voltages corresponding to 16 steps, the trimming circuit 20 requires 16 pairs of division resistors R1-I (I=1, 2, . . . , m). and MOS transistors Ti, 16 interconnections for control signals Di to be input to the gates of the MOS transistors Ti, and 16 4-input decoder circuits each serving as the decoder circuit 21 for decoding 4-bit digital data.
In general, if a trimming step count is 2N, 2N division resistors and 2N N-input decoders corresponding to N-bit digital inputs are required.
As the value of N increases, the number of elements such as the decoder circuits 21 and division resistors abruptly increases. As a consequence, the pattern area of the trimming circuit 20 increases, resulting in difficulty in circuit design. In addition, the degree of freedom in pattern change is low with respect to manufacturing variations in resistance value. This makes it more difficult to make a design change for the adjustment of resistance values.
A conventional multi-level high power generating circuit for an EEPROM to which the internal voltage generating circuit is applied will be described next.
Among EEPROMs, a NAND cell type flash memory using an array of cell units (NAND cells) each consisting of a plurality of series-connected memory cells is known as a memory that allows high integration and batch erase operation.
Each memory cell of a NAND cell type flash memory has a MOSFET structure in which a floating gate (charge storage layer) and a control gate are stacked, through an insulating film, on a semiconductor substrate on which source and drain regions are formed. A NAND cell is formed by connecting a plurality of memory cells in series with each other with adjacent memory cells sharing sources and drains. Such NAND cells are arranged in the form of a matrix to form one memory cell array.
In this case, the respective bit lines extend in the column direction, and the drain on one end side of each of NAND cells arranged side by side in the column direction of the memory cell array is commonly connected to the bit lines through a corresponding selection gate transistor. The source on the other end side of each NAND cell is connected to a common source line through a corresponding selection gate transistor. The control gates of the respective cell transistors are continuously arranged in the row direction to serve as control gate lines (word lines), and the gates of the respective selection gate transistors are continuously arranged in the row direction to serve as selection gate lines.
Such a NAND cell type flash memory is disclosed in K. D. Suh et al., xe2x80x9cA3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,xe2x80x9d IEEE J. Solid-State Circuits, vol. 30, No. 11, pp. 1149-1156, November 1995 and the like.
FIG. 7 in the above reference shows circuits having arrangements like those shown in FIG. 7 as a Vpgm generating circuit (step-up circuit) for generating a write voltage Vpgm to be applied to a word line and the like in data write or erase operation and a voltage limiter circuit.
Referring to FIG. 9A, the voltage limiter circuit connected between the output node (Vpgm node) of a Vpgm charge pump circuit 100 and a ground potential Vss is comprised of a voltage generating circuit section, a voltage comparison circuit section, and the like.
The above voltage generating circuit section is made up of a plurality of voltage dividing resistors Ri (R12 to R1 in this case) connected in series, one NMOS transistor Qn0, and a plurality of switch selection NMOS transistors Qni (Qn1 to Qn10 in this case) each having one terminal connected to one terminal each of some resistors (R10 to R1 in this case) and the other terminal commonly connected.
The gates of the NMOS transistors Qn1 to Qn10 respectively receive corresponding control signals TRMI (TRM1 to TRM10 in this case). The gate of the NMOS transistor Qn0 receives a control signal PGM.
The above voltage comparison circuit section is a differential operational amplification circuit made up of PMOS transistors Qp1 and Qp2 and NMOS transistors Qn21, Qn22 and Qn23. The voltage at the connection node between the resistors R11 and R12 of the voltage generating circuit section is applied to the gate of the NMOS transistor Qn22 which is one of the driving MOS transistors. The reference voltage Ref generated by a reference voltage generating circuit (not shown) is applied to the gate of the NMOS transistor Qn21 which is the other driving MOS transistor. The reference voltage Ref is then compared with the potential at the connection node between the resistors R11 and R12.
The above control signal PGM is supplied to the gate of the NMOS transistor Qn23 in the voltage comparison circuit section. When this signal PGM is set at xe2x80x9cHxe2x80x9d level to turn on the NMOS transistor Qn23 the voltage comparison circuit performs comparing operation.
The signal from the output node of the voltage comparison circuit section and the control signal PGM are input to an 2-input NAND circuit 101. The output from the NAND circuit 101 is input to a clock output circuit 102. The output from the NAND circuit 101, input to the clock output circuit 102, is controlled by clock signals xcfx86p and {overscore (xcfx86p)} and output as output signals xcfx86 vpgm and {overscore (xcfx86vpgm)}.
In the voltage limiter circuit having the above arrangement, it is checked whether the potential at the connection node between the resistors R11 and R12 is higher or lower than the reference voltage Ref. In accordance with the determination result, the output signals xcfx86 vpgm and {overscore (xcfx86vpgm)} are activated, and the operation of the Vpgm charge pump circuit 100 is controlled to be inactivated/activated. As a result, the Vpgm node is kept at a nearly constant voltage (limit voltage).
The potential difference between the potential at the Vpgm node and the ground potential Vss is divided into a plurality of potential difference outputs by the resistors R12 to R1. These potential difference outputs are controlled such that one of the switch selection transistors Qn1 to Qn10 is turned on in accordance with the control signals TRM1 to TRM10. The limit voltage setting values can therefore be adjusted by changing the settings of the control signals TRM1 to TRM10.
More specifically, as shown in FIG. 9B, when the transistor Qn1 is selected, a voltage of 16.0V is generated. When the transistor Qn2 is selected, a voltage of 16.5V is generated. When the transistor Qn10 is selected, a voltage of 20.0V is generated. This circuit can generate different output voltages ranging from 15.5V to 20.0V in steps of 0.5V.
The voltage limiter circuit in FIG. 9A, however, has the following problems.
First, the control signals TRM1 to TRM10 are decoded signals, and one decoder is required for one control signal TRMi. Therefore, as the number of output voltage steps increases, the number of decoders increases, resulting in an increase in pattern area.
In addition, when the set values of output voltages need to be changed in accordance with write/erase characteristics of memory cells, since the degree of freedom in setting output voltages is low, all the resistance values must be changed in some case. When the number of output voltage steps is large, in particular, it is difficult to finely adjust or correct all the resistance values.
As schemes of solving the above problem of an increase in pattern area, several schemes are known, in which signals are directly decoded in an analog fashion by combining resistors such as current addition type D/A conversion circuits, voltage addition type D/A conversion circuits, weighted resistance type D/A conversion circuits, and the like without using any decoders.
Of these circuits, current addition type D/A conversion circuits are used most widely. The operation principle of this scheme is disclosed in, for example, Toshikazu Yoneyama, xe2x80x9cIllustration: Introduction to D/A Conversionxe2x80x9d, OHM-Sha, Ltd., 1993.
As described above, in the voltage limiter circuit of the conventional internal voltage generating circuit, the degree of freedom in determining a set voltage range, the minimum set voltage, and the number of voltage steps is low. If, therefore, the minimum set voltage changes, the number of voltage steps changes. In addition, since the trimming decoder circuit must generate control signals equal in number to set voltages, the arrangement is complicated, and the number of elements used increases.
The present invention has been made to solve the above problems, and has as its object to provide an internal voltage generating circuit which can independently set the minimum set voltage and a voltage step width, shift the set voltage range while keeping the voltage step with constant, and set 2n voltage values by using n control signals without using any trimming decoding circuits.
It is another object of the present invention to provide a semiconductor memory which can relatively easily output positive multi-level voltages between a reference potential and a higher power supply potential by using a current addition type D/A conversion circuit, and suppress an increase in the proportion of the pattern area of a resistor network even if a bit count n of a digital input increases.
According to the present invention, there is provided an internal voltage generating circuit comprising a charge pump circuit, a load resistor element having one terminal connected to an output node of the charge pump circuit, a first voltage setting circuit which is connected to a first node to which the other terminal of the load resistor element is connected and controls a magnitude of an input current from the load resistor element by controlling an equivalent resistor in accordance with digital data, a second voltage setting circuit which is connected to the first node to which the other terminal of the load resistor element is connected and into which a predetermined current flows from the load resistor element, a potential comparison circuit for detecting a potential at the first node by comparing the potential at the first node with a reference potential, and a charge pump control circuit for setting the potential at the first node to become equal to the reference potential by substantially controlling the charge pump circuit in accordance with an output from the potential comparison circuit.
In addition, according to the present invention, there is provided a semiconductor memory comprising an oscillation circuit whose oscillation operation is allowed/inhibited in accordance with an oscillation enable signal, the oscillation circuit being adapted to generate a clock signal having a predetermined period in an oscillation operation state, a charge pump circuit for generating a predetermined high voltage by boosting a power supply voltage in accordance with the clock signal, a load resistor element having one terminal connected to an output node of the charge pump circuit, a first voltage setting circuit which is connected to a first node to which the other terminal of the load resistor element is connected and controls a magnitude of an input current from the load resistor element by controlling an equivalent resistor in accordance with digital data, a second voltage setting circuit which is connected to the first node to which the other terminal of the load resistor element is connected and into which a predetermined current flows from the load resistor element, an operational amplification circuit for comparing a potential at the first node with a predetermined reference potential, and controlling an active/inactive state of an oscillation enable signal from the oscillation circuit in accordance with a comparison result, and a memory cell array constituted by memory cells in/from which data is written/erased by using an output voltage from the charge pump circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.